Condor Computing

Condor Currents

Technology EN ↓ Odcinki: 82

Condor Currents delivers concise breakdowns of the latest computer architecture research and RISC-V developments. Each episode covers recent arXiv papers on data prefetching, branch prediction, and microarchitecture innovations, plus news from the open silicon community. Brought to you by Condor Computing, high-performance RISC-V processor IP from Andes Technology.

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Autor

Condor Computing

Kategoria

Technology

Strona podcastu

limitless-ai-podcasts.s3.us-east-2.amazonaws.com

Ostatni odcinek

10 lip 2026

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Odcinki

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings 19.03.2026

## Episode Summary In this episode, we cover: - **Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings** (arXiv) - **RAGPerf: An End-to-End Benchmarking Framework for Retrieval-Augmented Generation Systems** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of...

A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency 18.03.2026

## Episode Summary In this episode, we cover: - **A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency** (arXiv) - **Dynamic Sparse Attention: Access Patterns and Architecture** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference...

Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage 17.03.2026

## Episode Summary In this episode, we cover: - **Machine Learning-Driven Intelligent Memory System Design: From On-Chip Caches to Storage** (arXiv) - **Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (go...

RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual 15.03.2026

## Episode Summary In this episode, we cover: - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_news) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_...

RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual 14.03.2026

Multi-Agent Memory from a Computer Architecture Perspective: Visions and Challenges Ahead 13.03.2026

## Episode Summary In this episode, we cover: - **Multi-Agent Memory from a Computer Architecture Perspective: Visions and Challenges Ahead** (arXiv) - **The $qs$ Inequality: Quantifying the Double Penalty of Mixture-of-Experts at Inference** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **The Evolution of CPU Architectures...

Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques 12.03.2026

## Episode Summary In this episode, we cover: - **Mitigating the Memory Bottleneck with Machine Learning-Driven and Data-Aware Microarchitectural Techniques** (arXiv) - **Pooling Engram Conditional Memory in Large Language Models using CXL** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **RISC-V Vector Extension: Between standardization and...