Condor Currents

## Episode Summary In this episode, we cover: - **Vectorizing Quantum Control: A RISC-V Vector Extension Architecture for Scalable Qubit Systems** (arXiv) - **Memory Scarcity, Open Models, and the Restructuring of the AI Industry, 2026-2030 -- A quantitative scenario analysis of inference economics, training-cost divergence, and infrastructure solvency** (arXiv) - **RISC-V Vector Engine Addresses...

## Episode Summary In this episode, we cover: - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - AOL.com** (google_riscv) - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **Zhihe A210 octa-core RISC-V SoC wi...

## Episode Summary In this episode, we cover: - **TileLens: Efficiently Using Large-Granularity Memory Systems with Transparent Two-Dimensional Memory Layout** (arXiv) - **Bounded-Memory Parallel Image Pulling for Large Container Images** (arXiv) - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Dej...

## Episode Summary In this episode, we cover: - **A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration** (arXiv) - **ELiTeFormer: An Efficient Transformer for FPGAs** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoron...

## Episode Summary In this episode, we cover: - **A Multi-Dimensional, Per-Pass Empirical Study of the LLVM Optimization Pipeline** (arXiv) - **Approximate Attention Weighting for Sustainable FPGA-Based Vision Transformer Inference** (arXiv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Architecture Wi...

## Episode Summary In this episode, we cover: - **The Fourth-Root Complexity of Data Movement** (arXiv) - **Dynamic Ultrasound Beamforming Using Left-to-Right Arithmetic Adders on FPGA** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **QuMA: Researchers Develop Quantum Microarchitecture that "Bridges the Gap" in Processor System S...

## Episode Summary In this episode, we cover: - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Synergy Quantum Unveils Quantum-Safe Silicon IP Cores for RISC-V-Based SoCs - The Trib...

## Episode Summary In this episode, we cover: - **3DLS: A 3D Logic-Stacked Architecture for Disaggregated LLM Serving** (arXiv) - **KernelSight-LM: A Kernel-Level LLM Inference Simulator** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Synergy Quantum Unveils...

## Episode Summary In this episode, we cover: - **High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture** (arXiv) - **KernelSight-LM: A Kernel-Level LLM Inference Simulator** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Sipeed launches K3 Pico-ITX and CoM260 bo...

## Episode Summary In this episode, we cover: - **TraceLab: Characterizing Coding Agent Workloads for LLM Serving** (arXiv) - **Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon** (arXiv) - **RISC-V Soft Processor System on DE10-Lite - Hackster.io** (google_riscv) - **Now you can put a SpacemiT K3 RISC-V processor in a Framework Laptop 13 - Liliput...

## Episode Summary In this episode, we cover: - **HBM Is Not All You Need: Efficient Disaggregated LLM Serving across Memory-heterogeneous Accelerators** (arXiv) - **TraceLab: Characterizing Coding Agent Workloads for LLM Serving** (arXiv) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based development board - CNX Software** (google_riscv) - **Using a Performance Model to Impleme...

## Episode Summary In this episode, we cover: - **CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation** (arXiv) - **Phase Matters: Characterizing Heterogeneous Vision-Language Inference on a Mobile SoC** (arXiv) - **AI is stress-testing processor architectures and RISC-V fits the moment - EDN - Voice of the Engineer** (google_riscv) - **Milk-V Jupi...

## Episode Summary In this episode, we cover: - **SOLAR: AI-Powered Speed-of-Light Performance Analysis** (arXiv) - **Accelerating Disaggregated RL for Visual Generative LLMs with Diffusion-Based Parallelism and Trainer-Assisted Generation** (arXiv) - **Security Researchers Find Current RISC-V CPU Implementations Coming Up Short - Phoronix** (google_riscv) - **SiFive Upgrades P500 RISC-V IP Cores...

## Episode Summary In this episode, we cover: - **The Serialized Bridge: Understanding and Recovering LLM Serving Performance under Blackwell GPU Confidential Computing** (arXiv) - **Learning Filters with Certainty** (arXiv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V CPU - TechPowerUp** (google_riscv) - **Prompt to tape out: Autonomous AI agent builds 1.5 GHz RISC-V CPU -...

## Episode Summary In this episode, we cover: - **CVA6-RT: an Open-Source Time-Predictable RV64 Processor for Mixed-Criticality Systems** (arXiv) - **Residual GPU Cache State on Apple M4 Pro** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DH...

## Episode Summary In this episode, we cover: - **Cache-Resident LLM Inference in GB-Scale Last-Level Caches** (arXiv) - **Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **China's LineShine tops supercomputer ranking with all-CPU architecture - China Daily** (google_arch) - **How...

## Episode Summary In this episode, we cover: - **CrossPool: Efficient Multi-LLM Serving for Cold MoE Models through KV-Cache and Weight Disaggregation** (arXiv) - **2.5D Root of Trust: Securing the Chiplet Ecosystem** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **Zhihe A210 octa-core RISC-V SoC with 12 TOPS NPU powers SoM-based developme...

## Episode Summary In this episode, we cover: - **Non-Uniform L2 Cache Latency Across the Streaming Multiprocessors of an NVIDIA L40** (arXiv) - **MOCAP: Wafer-Scale-Chip-Oriented Memory-Orchestrated Chunked Pipelining Framework for Prefill-Only LLM Inference** (arXiv) - **Software to Silicon With RISC-V for Physical AI** (eetimes) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-T...

## Episode Summary In this episode, we cover: - **UltraQuant: 4-bit KV Caching for Context-Heavy Agents** (arXiv) - **Fractional Verkle Trees: A Hypertree Decomposition and Verified Proof Serialization Architecture for High-Performance Blockchain State Accumulators** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - RedShark News** (google_arch) - **Initial Benchmarks Of The Spa...

## Episode Summary In this episode, we cover: - **Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge** (arXiv) - **From the NYU Ultracomputer to Modern Exascale: A Historical and Architectural Survey of In-Network Computing and Scalable Synchronization** (arXiv) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (go...

## Episode Summary In this episode, we cover: - **AIA: A Customized Multi-core RISC-V SoC for Discrete Sampling Workloads in 16 nm** (arXiv) - **AIA: A 16nm Multicore SoC for Approximate Inference Acceleration Exploiting Non-normalized Knuth-Yao Sampling and Inter-Core Register Sharing** (arXiv) - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv...

## Episode Summary In this episode, we cover: - **SMEPilot: Characterizing and Optimizing LLM Inference with Scalable Matrix Extensions** (arXiv) - **The Price of Anarchy in Disaggregated Inference** (arXiv) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference Manual** (riscv_news) - **One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon** (riscv_new...

## Episode Summary In this episode, we cover: - **A Spatio-Temporal Expert Prefetching Framework for Efficient MoE-based LLM Inference** (arXiv) - **MADAR: An Address-Free Processor** (arXiv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **Synergy Quantum Unveils Quan...

## Episode Summary In this episode, we cover: - **Tiara: A Programmable Line-Rate ISA for Remote Memory Access** (arXiv) - **HierSVA: A Data Synthesis Pipeline, Dataset, and Benchmark for LLM-Driven Hierarchical Hardware Formal Verification** (arXiv) - **Using a Performance Model to Implement a Superscalar CVA6** (riscv_news) - **Ben C.'s Clever Compiler Imports Verilog Designs, Including a Workin...

## Episode Summary In this episode, we cover: - **Isolation-aware Scheduling Framework for DNN-based End-to-End Autonomous Driving System on Tile-based Accelerators** (arXiv) - **Non-Parametric Dual-Manifold Mapping via 8-Bit Bounded Transformation Matrices: Challenging FP-centric Hardware Paradigms in Low-Energy AI** (arXiv) - **160-core RISC V Board Is The M.2 CoProcessor You Didn’t Know You Nee...