Condor Currents

## Episode Summary In this episode, we cover: - **Energy-Efficient On-Device RAG on a Mobile NPU: System Design and Benchmark on Snapdragon X Elite** (arXiv) - **A Hybrid Edge-Cloud Architecture for Low-Latency Entitlement Verification in Resource-Constrained Devices** (arXiv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - TechPowerUp** (google_r...

## Episode Summary In this episode, we cover: - **SupraSNN: Exploiting Synapse-Level Parallelism in Spiking Neural Network Accelerators through Co-Optimized Mapping and Scheduling** (arXiv) - **Partitioned Tags, Shared Data: Reconciling Strict Cache Isolation with Write-Shared Coherence** (arXiv) - **Intel Panther Lake Technical Deep Dive - Compute Tile: CPU Architecture - TechPowerUp** (google_ar...

## Episode Summary In this episode, we cover: - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC - Business Wire** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (google_riscv) - **NextSilicon Productizes Arbel RISC-V Core Into 64-Core Enterprise Processor - Quantum Zeitgeist** (goog...

## Episode Summary In this episode, we cover: - **Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques** (arXiv) - **SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC** (arXiv) - **The RISC-V Vector Extensions for AI - Jon Peddie Research** (google_riscv) - **NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Proce...

## Episode Summary In this episode, we cover: - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **NetKV: Network-Aware Decode Instance Selection for Disaggregated LLM Inference** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_arch) - **As Alibaba launches server-grade RISC-V CPU, Beiji...

## Episode Summary In this episode, we cover: - **ANNS-AMP: Accelerating Approximate Nearest Neighbor Search via Adaptive Mixed-Precision Computing** (arXiv) - **MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC) - Semiconductor Engineering** (google_ris...

## Episode Summary In this episode, we cover: - **BIDENT: Heterogeneous Operator-level Mapping for Efficient Edge Inference** (arXiv) - **Multi-Segment Attention: Enabling Efficient KV-Cache Management for Faster Large Language Model Serving** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX - Phoronix** (google_riscv) - **A Deep Dive Into CPU Architecture -...

## Episode Summary In this episode, we cover: - **AheadComputing Introduces Breakthrough CPU Architecture for General-Purpose Computing, With Jim Keller on Board - TechPowerUp** (google_arch) - **Deja Vu: A Brief History of Every Mac CPU Architecture - How-To Geek** (google_arch) - **How RISC-V CPUs and GPUs Are Reshaping High-Performance SoCs in 2026 - News and Statistics - IndexBox** (google_ris...

## Episode Summary In this episode, we cover: - **Migration Using Context Cache for Multicore RISC‐V Processor - Wiley Online Library** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **Performance aware shared memory hierarchy model for multicore processors - Nature** (google_arch) - **RISC-V vs ARM: Which Instruction Set Archite...

## Episode Summary In this episode, we cover: - **Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees** (arXiv) - **The key CPU architecture you've never heard of: RISC-V - Red Shark News** (goog...

## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **White paper: The All-...

## Episode Summary In this episode, we cover: - **Regular-Dead on Arrival: Characterizing and Protecting Against Dead-Entry TLB Misses in GPU Microarchitectures** (arXiv) - **Observation, Not Prediction: Conversation-Level Disaggregated Scheduling for Agentic Serving** (arXiv) - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **RISC-V...

## Episode Summary In this episode, we cover: - **FREESS: A Web-Based Educational Simulator for a RISC-V-Inspired Superscalar Processor with Tomasulo-Style Dynamic Scheduling** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **Evaluating RISC-V Vector Processors: GCC vs. LLVM Autovectorization Benchmarks (May 2026) - News and Statistics - IndexBox** (google_riscv) - *...

## Episode Summary In this episode, we cover: - **Co-Designing Graph-based Approximate Nearest Neighbor Search at Billion Scale for Processing-in-Memory** (arXiv) - **Code size reduction by advanced near addressing modes** (arXiv) - **AI agent designs complete RISC-V CPU core autonomously - MSN** (google_riscv) - **CPU Instruction Set Architecture (ISA) Market - Market Growth Reports** (google_arc...

## Episode Summary In this episode, we cover: - **Sustainable Real-Time 8K60 HEVC Encoding for V2X: Repurposing Legacy NVENC Hardware at the Vehicular Edge** (arXiv) - **PoisonCap: Efficient Hierarchical Temporal Safety for CHERI** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Desi...

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3...

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3...

## Episode Summary In this episode, we cover: - **Accelerating State-Vector Quantum Simulation on Integrated GPUs via Cache Locality Optimization: A Cross-Architecture Evaluation** (arXiv) - **NasZip: Software and Hardware Co-Design to Accelerate Approximate Nearest Neighbor Search with DIMM-Based Near-Data Processing** (arXiv) - **Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3...

## Episode Summary In this episode, we cover: - **OSCAR: Offline Spectral Covariance-Aware Rotation for 2-bit KV Cache Quantization** (arXiv) - **TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing** (arXiv) - **Four-Tier Memory Hierarchy for LLM Reasoning (USC, UW)** (semiengineering) - **As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA - The R...

## Episode Summary In this episode, we cover: - **How Did An AI Agent Build a RISC V CPU Core In Just 12 Hours - IEEE Spectrum** (google_riscv) - **India unveils a homegrown dual-core 1GHz RISC-V processor, the DHRUV64 - The Register** (google_riscv) - **AI designs complete RISC-V CPU core in just 12 hours - MSN** (google_riscv) - **India Launches DHRUV64, Its First 1 GHz, 64-bit Dual-Core RISC-V...

## Episode Summary In this episode, we cover: - **Enhancing Instruction Prefetching via Cache and TLB Management** (arXiv) - **ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses** (arXiv) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (KTH, LLNL, BSC)** (semiengineering) - **Evaluating and Calibrating Performance On RISC-V Vector Processors (K...

## Episode Summary In this episode, we cover: - **SpacemiT K3 “16-core” RISC-V SoC system information and (early) benchmarks - CNX Software** (google_riscv) - **Nvidia's CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm - Tom's Hardware** (google_riscv) - **Bit-Brick K1: Raspberry Pi 5 alternative with different CPU architecture, M....

## Episode Summary In this episode, we cover: - **RISC-V set to announce 25% market penetration — open-standard ISA is ahead of schedule, securing fast-growing silicon footprint - Tom's Hardware** (google_riscv) - **The Evolution of CPU Architectures – From Intel 4004 To Modern SoCs - Wccftech** (google_arch) - **China claims to have developed the world's first AI-designed processor — LLM turned p...

## Episode Summary In this episode, we cover: - **RISC-V Vector Extension: Between standardization and tailor-made accelerators - eeNews Europe** (google_riscv) - **Checking In On The ISA Wars And Its Impact On CPU Architectures - Hackaday** (google_arch) - **Support RAJA and Scientific Applications on RVV Architectures** (riscv_news) - **RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than...

## Episode Summary In this episode, we cover: - **SPEC CPU2026: Characterization, Representativeness, and Cross-Suite Comparison** (arXiv) - **Beyond Static Policies: Exploring Dynamic Policy Selection for Single-Thread Performance Optimization** (arXiv) - **RISC-V: The Open-Source Revolution in CPU Architecture - Design And Reuse** (google_riscv) - **RISC-V: The Open-Source Revolution in CPU Arch...