Zero to ASIC Course

January news update! MPW1 silicon & bringup, MPW4 submitted, MPW5 tapeout

Carlos' twitter space: https://twitter.com/carlosedp/status/1469355189891125255 Silicon compiler: https://www.siliconcompiler.com/ Amaranth: https://github.com/amaranth-lang/amaranth MPW2 rerun: https://efabless.com/projects/585 MPW4 application: https://efabless.com/projects/596 Caravel restructure: https://github.com/efabless/caravel SkullFET: https://twitter.com/UriShaked/status/147225897250581...

MPW3 App: SoC https://efabless.com/projects/481 SoC source: https://github.com/ChipFlow/caravel_user_project_mpw3.git Amaranth: https://github.com/amaranth-lang/amaranth

In this interview we talk about Staf's recent tapeout, the flexcell standard cell generator and pdk master - a kind of API for pdks. Staf also gives his opinions on the state of the industry and whether we at an inflection point for open source silicon.

Lots of open source ASIC news from November. Check the youtube description for all the links. https://youtu.be/goOzeELjjnI

In this interview with Matt Guthaus, we talk about: Recap - what is OpenRAM Why do we need a memory compiler like OpenRAM? 3 phases of OpenRAM development What’s changed since FOSSi dialup MPW2 tapeout of OpenRAM Test modes What was hard about MPW2 DRC issues Status of OpenLANE support for OpenRAM Future plans for OpenRAM Access to resistive RAM, hopefully for MPW4

Tom Spyrou is a long time EDA developer who has worked at large and small companies. In 1988 Developed QTV at VLSI technology. It was the first STA engine to be trusted to sign off devices for fabrication without timing based simulation. He was the original architect of PrimeTime STA algorithm. Manager of Cadence Common timing Engine and precursor to Open Access Senior technical positions at Synop...

One of the popular types of entries to MPW1 & 2 have been FPGAs. I have previously spoken with Arya Reais-Parsi about their FPGA project submitted to MPW1. In MPW2 I noticed there were a couple of applications that seemed fairly advanced - especially FuseRISC: 2 RISCV processors with embedded FPGA fabric between them.

Will Green: learning FPGAs with graphics and project F

00:00 Introducing Dan Rodrigues 01:15 Dan was on the first shuttle 02:30 Converting an FPGA project to an ASIC 03:17 How long it took to prepare his submission? 05:17 What kind of config changes were required? 07:50 VDP-lite - wishbone peripheral that can generate sprites and put out on VGA: https://github.com/dan-rodrigues/caravel_vdp_lite 08:45 No framebuffer 11:20 How many flip flops were requi...

00:00 Introducing Thomas Parry 00:36 Project is an amateur satellite transceiver 01:02 Thomas wanted a challenging project 01:17 His background 01:50 Working for SystematIC Design in Delft doing analogue chip design 02:29 Design split into 2 repositories, see links below 03:50 Day to day work with Cadence and MentorGraphics industry standard tools 04:25 Pay money to reduce risk - no one to shout a...

In this interview Sylvain talks about: 1:15 ? why he's excited about the shuttle 4:00 ? what is the design he's working on 8:00 ? expectation vs experience with the Open Source ASIC tools 8:57 ? a look at the final GDS files 14:20 ? differences between design for ASIC vs FPGA 16:38 ? tap cells 17:50 ? antenna rules Sylvain's previous streams on the Skywater 130nm PDK: https://www.youtube.com/watch...

1:00 ? What made you excited about the shuttle? 2:22 ? The spectrometer design - radar signal processing 4:00 ? built in self test 4:18 ? in & output signals 6:00 ? design in Chisel 10:40 ? ASIC vs FPGA 11:30 ? showing the GDS 12:24 ? density of the design 13:30 ? contact details https://github.com/milovanovic/spectr... ? https://www.zerotoasic.com/ ?

In this interview Arya Reais-Parsi talks about: 00:45 ? FPGA design is for a course 01:50 ? difference between other open FPGA fabrics 02:50 ? FPGAs as accelerators 04:27 ? their FPGA structure 06:30 ? how did they target ASIC? 09:27 ? GDS view of the FPGA structure 11:40 ? custom cells for FPGAs 14:40 ? making lab notes 16:00 ? how does actually taping something out change the feeling of the work...

00:36 ? Diego's background 01:30 ? choice of design and the new tools 02:50 ? digital vs analog process 09:05 ? op-amp specifications 12:35 ? schematic in xschem 13:40 ? open loop testbench 14:26 ? spice setup 15:37 ? simulation results 17:44 ? layout in magic 23:20 ? opamps placed in the user project wrapper of Caravel 27:20 ? testing the ASIC Diego on linked.in: https://www.linkedin.com/in/diego...

00:00 ? introduction 01:04 ? worked under Kunal Ghosh as an intern: https://www.vlsisystemdesign.com/basi... ? 02:18 ? Questions from Niklas - time it takes, what's frustrating, fun? 05:40 ? Are the tools ready for mixed signal designs - DRC violations in Caravel. 07:20 ? Question from Pepijn - what would you need to change to alter the PLL? 08:44 ? PLL overview 10:00 ? Lakshmi's design: Frequency...

https://github.com/antonblanchard/microwatt-caravel

00:12 Tim Edwards introduction 01:00 next steps after submission before files sent to Skywater 02:00 infrastructure - getting all the latest from everyone's repositories 03:05 size of the repos can be a problem 03:41 revolutionary part of this run is that everything is Open Source down to the GDS 04:51 Open Source PDK is what makes it possible to do this for eFabless 05:12 Why didn't we submit the...